M74HCT646 Datasheet, PDF (1/12 Pages) STMicroelectronics – HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.

M74HCT646
M74HCT648
HCT646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
HCT648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
. HIGH SPEED
f_MAX = 60 MHz (TYP.) AT V_CC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
I_OH= I_OL = 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS646/648
B1R
(Plastic Package)
M1R
(Micro Package)
ORDER CODES :
M74HCTXXXM1R M74HCTXXXB1R
DESCRIPTION
The M74HCT646/648 are high speed CMOS
OCTAL BUS TRANSCEIVERS AND REGISTERS,
(3-STATE) fabricated in silicon gate C²MOS tech-
nology. They have the same high speed
performance of LSTTL combined with true CMOS
low power consumption. These devices consist of
bus transceiver circuits with 3-state output, D-type
flip-flops, and control circuitry arranged for multi-
plexed transmission of data directly from the input
bus or from the internal registers. Data on the A or
B bus will be clocked into the registers on the low-
to-high transition of the appropriate clock pin (Clock
AB - or Clock BA). Enable (G) and direction (DIR)
pins are provided to control the transceiver function-
s. In the transceiver mode, data present at the
high-impedance port may be stored in either register
or in both. The select controls (Select AB select BA)
can multiplex stored and real-time (transparent
mode) data. The direction control determines which
bus will receive data when enable G is active (low).
In the isolation mode (enable G high), ”A” data may
be stored in one register and/or ”B” data may be
stored in the other register. When an output function
is disabled, the input function is still enabled and
may be used to store and transmit data. Only one
of the two buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M74HCT devices are de-
signed to directly interface HSC²MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
GAB, GAB, CAB,
A, B
SAB, SBA, CBA
October 1993
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