M74HCT373 Datasheet, PDF (1/11 Pages) STMicroelectronics – OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

M74HCT373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
t_PD = 19ns (TYP.) at V_CC = 4.5V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s COMPATIBLE WITH TTL OUTPUTS :
V_IH = 2V (MIN.) V_IL = 0.8V (MAX)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 6mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
DESCRIPTION
The M74HCT373 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with sub-micron silicon gate C²MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the logic
level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
TSSOP
M74HCT373B1R
M74HCT373M1R M74HCT373RM13TR
M74HCT373TTR
level) and when OE is in high level the outputs will
be in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
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