M74HCT138 Datasheet, PDF (1/9 Pages) STMicroelectronics – 3 TO 8 LINE DECODER (INVERTING)

M74HCT138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED:
t_PD = 16ns (TYP.) at V_CC = 4.5V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s COMPATIBLE WITH TTL OUTPUTS :
V_IH = 2V (MIN.) V_IL = 0.8V (MAX)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
DESCRIPTION
The M74HCT138 is an high speed CMOS 3 TO 8
LINE DECODER fabricated with silicon gate
C²MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go high. Three
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
TSSOP
M74HCT138B1R
M74HCT138M1R M74HCT138RM13TR
M74HCT138TTR
enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
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