M74HC77 Datasheet, PDF (1/10 Pages) STMicroelectronics – 4-BIT D-TYPE LATCH

M74HC77
4 BIT D TYPE LATCH
s HIGH SPEED :
t_PD = 11 ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 77
DESCRIPTION
The M74HC77 is an high speed CMOS 4 BIT D
TYPE LATCH fabricated with silicon gate C²MOS
technology.
It contains two groups of 2 bit latches controlled by
an enable input (G1•2 or G3•4). These two latch
groups can be used in different circuits. The data
applied to the data inputs (1D, 2D, or 3D, 4D) are
transferred to the Q outputs (1Q, 2Q, or 3Q, 4Q)
respectively when the enable input (G1•2 or G3•4)
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC77B1R
M74HC77M1R
T&R
M74HC77RM13TR
M74HC77TTR
is taken high. The Q outputs will follow the data
inputs as long as the enable input is kept high.
When the enable input is taken low, the
information data applied to the data input is
retained at the Q outputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
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