M74HC76-1 Datasheet, PDF (1/11 Pages) STMicroelectronics – DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC76
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED :
f_MAX = 67MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 76
DESCRIPTION
The M74HC76 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C²MOS technology.
Depending on with the logic level at J and K
inputs, this device changes state on the negative
going transition of clock pulse (CK). CLEAR (CLR)
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC76B1R
M74HC76M1R
T&R
M74HC76RM13TR
M74HC76TTR
and PRESET (PR) are independent of the clock
and are accomplished by a logic low on the
corresponding input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/11