M74HC75 Datasheet, PDF (1/9 Pages) STMicroelectronics – 4 BIT D TYPE LATCH

. HIGH SPEED
tPD = 10 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 2 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC = (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS75
DESCRIPTION
The M54/74HC75 is a high speed CMOS 4-BIT D-
TYPE LATCH fabricated in silicon gate C²MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. It contains two groups of 2-bit latches con-
trolled by an enable input (G1•2 or G3•4). These two
latch groups can be used in different circuits. Each
latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q).
The data applied to the data input is transfered to the
Q and Q outputs when the enable input is taken high
and the outputs will follow the data input as long as
the enable input is kept high. When the enable input
is taken low, the information data applied to the data
input is retained at the outputs. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
M54HC75
M74HC75
4 BIT D TYPE LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC75F1R
M 74H C7 5M 1R
M 74HC 75 B1 R
M 74H C7 5C 1R
PIN CONNECTIONS (top view)
December 1992
NC =
No Internal
Connection
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