M74HC533 Datasheet, PDF (1/11 Pages) STMicroelectronics – OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING

M74HC533
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT INVERTING
s HIGH SPEED:
t_PD = 12ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 6mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 533
DESCRIPTION
The M74HC533 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C²MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input. When the LE is
taken, the Q outputs will be latched at the logic
level of D input data.
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC533B1R
M74HC533M1R
T&R
M74HC533RM13TR
M74HC533TTR
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/11