M74HC4515 Datasheet, PDF (1/10 Pages) STMicroelectronics – HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH (INV.)

M74HC4514
M74HC4515
HC4514: 4 TO 16 LINE DECODER/LATCH
HC4515: 4 TO 16 LINE DECODER LATCH (INV.)
. HIGH SPEED
tPD = 18 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC(OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
4514B/4515B
B1R
(Plastic Package)
M 1R
(Micro Package)
ORDER CODES :
M 7 4H CX XXXM 1R
M74HCXXXXB1R
PIN CONNECTIONS (top view)
HC4514
DESCRIPTION
The 74HC4514 and the 74HC4515 are high speed
CMOS 4-LINE TO 16-LINE DECODERS WITH
LATCHED INPUTS fabricated in silicon gate
C²MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
A binary code stored in the four input latches (A to
D) provides a high level (HC4514) or a low level
(HC4515) at the selected one of sixteen outputs ex-
cluding the other fifteen outputs, when the inhibit
input (INHIBIT) is held low. When the inhibit input is
held high, all outputs are kept low level (HC4514) or
high level (HC4515), while the latch function is avail-
able. The data applied to the data inputs are trans-
fered to the Q outputs of latches when the strobe
input is held high. When the strobe input is taken
low, the information data applied to the data input at
a time is retained at the output of the latches. All in-
puts are equipped with protection circuits against
static discharge and transient excess voltage.
HC4515
October 1993
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