M74HC4094 Datasheet, PDF (1/12 Pages) STMicroelectronics – 8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)

M74HC4094
8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
s HIGH SPEED :
f_MAX = 80 MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4094
DESCRIPTION
The M74HC4094 is an high speed CMOS 8 BIT
SIPO SHIFT LATCH REGISTER fabricated with
silicon gate C²MOS technology.
This device consists of an 8 bit shift register and
an 8 bit latch with 3 state output buffer. Data is
shifted serially trough the shift register on the
positive going transition of the clock input signal.
The output of the last stage (Qs) can be used to
cascade several devices.
Data on the Qs output is transferred to a second
output (Qs’) on the following negative transition of
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
TSSOP
M74HC4094B1R
M74HC4094M1R M74HC4094RM13TR
M74HC4094TTR
the clock input signal. The data of each stage of
the shift register is provided with a latch, which
latches data on the negative going transition of the
STROBE input signal. When the STROBE input is
held high, data propagates through the latch to a
3-state output buffer.
This buffer is enabled when OUTPUT ENABLE
input is taken high.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
January 2003
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