M74HC280 Datasheet, PDF (1/9 Pages) STMicroelectronics – 9 BIT PARITY GENERATOR

M74HC280
9 BIT PARITY GENERATOR
s HIGH SPEED :
t_PD = 22ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
DESCRIPTION
The M74HC280 is an high speed CMOS 9-BIT
PARITY GENERATOR fabricated with silicon gate
C²MOS technology.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and ΣEVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd, ΣODD
output is kept high and ΣEVEN output low.
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC280B1R
M74HC280M1R
T&R
M74HC280RM13TR
M74HC280TTR
Conversely, when the output is even, ΣEVEN
output is kept high and ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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