M74HC259 Datasheet, PDF (1/13 Pages) STMicroelectronics – 8 BIT ADDRESSABLE LATCH

M74HC259
8 BIT ADDRESSABLE LATCH
s HIGH SPEED :
t_PD = 20 ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 259
DESCRIPTION
The M74HC259 is an high speed CMOS 8 BIT
ADDRESSABLE LATCH fabricated with silicon
gate C²MOS technology.
The M74HC259 has single data input (D) 8 latch
outputs (Q0-Q7), 3 address inputs (A, B, and C),
common enable input (E), and a common CLEAR
input. To operate this device as an addressable
latch, data is held on the D input, and the address
of the latch into which the data is to be entered is
held on the A, B, and C inputs. When ENABLE is
taken low the data flows through to the addresses
output. The data is stored on the positive-going
edge of the ENABLE pulse. All unaddressed
latches will remain unaffected. With ENABLE in
the high state the device is deselected and all
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC259B1R
M74HC259M1R
T&R
M74HC259RM13TR
M74HC259TTR
latches remain in their previous state, unaffected
by changes on the data or address inputs. To
eliminate the possibility of entering erroneous data
into the latches, the ENABLE should be held high
(inactive) while the address lines are changing. If
ENABLE is held high and CLEAR is taken low all
eight latches are cleared to the low state. If
ENABLE is low all latches except the addressed
latch will be cleared. The addressed latch will
instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
July 2001
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