M74HC237 Datasheet, PDF (1/11 Pages) STMicroelectronics – 3 TO 8 LINE DECODER LATCH

M74HC237
3 TO 8 LINE DECODER LATCH
s HIGH SPEED:
t_PD = 16ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 237
DESCRIPTION
The M74HC237 is an high speed CMOS 3 TO 8
LINE DECODER fabricated with silicon gate
C²MOS technology.
When GL goes from low to high, the address
present at the select inputs (A, B, C) is stored in
the latches. As long as GL remains high no
address changes will be recognized. Output
enable controls, G1 and G2 control the state of the
outputs independently of the select or
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC237B1R
M74HC237M1R
T&R
M74HC237RM13TR
M74HC237TTR
latch-enable inputs. All of the outputs are low
unless G1 is high and G2 is low. The M74HC237
is ideally suited for the implementation of
glitch-free decoders in stored-address
applications in bus oriented systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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