M74HC165_08 Datasheet, PDF (1/21 Pages) STMicroelectronics – 8-bit PISO shift register

Features
■ High speed:
– t_PD = 15 ns (typ.) at V_CC = 6 V
■ Low power dissipation:
– I_CC = 4 μA (max.) at T_A = 25 °C
■ High noise immunity:
V_NIH = V_NIL = 28 % V_CC (Min.)
■ Symmetrical output impedance:
|I_OH| = I_OL = 4 mA (min)
■ Balanced propagation delays:
t_PLH ≅ t_PHL
■ Wide operating voltage range:
V_CC (opr) = 2 V to 6 V
■ Pin and function compatible with
74 series 165
Table 1. Device summary
Order code
M74HC165B1R
M74HC165RM13TR
M74HC165TTR
May 2008
M74HC165
8-bit PISO shift register
DIP-16
SO-16
TSSOP16
Description
The M74HC165 is a high speed CMOS 8-bit
PISO (parallel-in-serial-out) shift register
fabricated with silicon gate C²MOS technology.
This device contains eight clocked master slave
RS flip-flops connected as a shift register, with
auxiliary gating to provide overriding
asynchronous parallel entry. The parallel data
enter when the shift/load input is low and can
change while shift/load is low, provided that the
recommended set-up and hold times are
observed. For clocked operation, shift/load must
be high. The two clock inputs perform identically:
one can be used as a clock inhibit by applying a
high signal, to allow this operation clocking is
accomplished through a 2-input nor gate. To avoid
double clocking, however, the inhibit signal should
only go high while the clock is high. Otherwise the
rising inhibit signal causes the same response as
rising clock edge. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
Package
DIP-16
SO-16
TSSOP16
Packaging
Tube
Tape and reel
Tape and reel
Rev 5
1/21
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