M74HC165 Datasheet, PDF (1/12 Pages) STMicroelectronics – 8 BIT PISO SHIFT REGISTER

M74HC165
8 BIT PISO SHIFT REGISTER
s HIGH SPEED :
t_PD = 15ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 165
DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C²MOS technology.
This device contains eight clocked master slave
RS flip-flops connected as a shift register, with
auxiliary gating to provide over-riding
asynchronous parallel entry. Parallel data enters
when the shift/load input is low. The parallel data
can change while shift/load is low, provided that
the recommended set-up and hold times are
observed. For clocked operation, shift/load must
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC165B1R
M74HC165M1R
T&R
M74HC165RM13TR
M74HC165TTR
be high. The two clock input perform identically;
one can be used as a clock inhibit by applying a
high signal; to permit this operation clocking is
accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit
signal should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as rising clock edge.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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