M74HC138 Datasheet, PDF (1/10 Pages) STMicroelectronics – 3 TO 8 LINE DECODER (INVERTING)

M74HC138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED:
t_PD = 13ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
DESCRIPTION
The M74HC138 is an high speed CMOS 3 TO 8
LINE DECODER fabricated with silicon gate
C²MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC138B1R
M74HC138M1R
T&R
M74HC138RM13TR
M74HC138TTR
inhibited and all the 8 outputs go high. Three
enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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