M74HC112_01 Datasheet, PDF (1/12 Pages) STMicroelectronics – DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC112
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED :
f_MAX = 79MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 112
DESCRIPTION
The M74HC112 is an high speed CMOS DUAL
J-K FLIP-FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C²MOS technology.
The M74HC112 dual JK flip-flop features
individual J, K, clock, and asynchronous set and
clear inputs for each flip-flop. When the clock goes
high, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC112B1R
M74HC112M1R
T&R
M74HC112RM13TR
M74HC112TTR
may be allowed to change when the clock pulse is
high and the bistable will function as shown in the
truth table. Input data is transferred to the input on
the negative going edge of the clock pulse.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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