M65KG256AB Datasheet, PDF (1/51 Pages) STMicroelectronics – 256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM

M65KG256AB
256Mbit (4 Banks x 4M x 16)
1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM
PRELIMINARY DATA
Features summary
■ 256Mbit SYNCHRONOUS DYNAMIC RAM
– Organized as 4 Banks of 4MWords, each
16 bits wide
■ DOUBLE DATA RATE (DDR)
– 2 Data Transfers/Clock Cycle
– Data Rate: 266Mbit/s (max.)
■ SUPPLY VOLTAGE
– V_DD = 1.7 to 1.9V (1.8V typical in
accordance with JEDEC standard)
– V_DDQ = 1.7 to 1.9V for Inputs/Outputs
■ SYNCHRONOUS BURST READ AND WRITE
– Fixed Burst Lengths: 2, 4, 8, 16 Words
– Burst Types: Sequential and Interleaved.
– Clock Frequency: 133MHz (7.5ns speed
class)
– Clock Valid to Output Delay (CAS Latency):
3 at 133MHz
– Burst Read Control by Burst Read
Terminate and Precharge Commands
■ AUTOMATIC PRECHARGE
■ BYTE WRITE CONTROLLED BY LDQM AND
UDQM
■ LOW-POWER FEATURES:
– Partial Array Self Refresh (PASR)
– Automatic Temperature Compensated Self
Refresh (ATCSR)
– Driver Strength (DS)
– Deep Power-Down Mode
– Auto Refresh and Self Refresh
■ LVCMOS Interface Compatible with
Multiplexed Addressing
■ OPERATING TEMPERATURE
– - 30 to 85°C
Wafer
The M65KG256AB is only available as part of a multi-chip package Product.
February 2006
Rev 1.0
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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