M54HCT138_04 Datasheet, PDF (1/10 Pages) STMicroelectronics – RAD HARD 3 TO 8 LINE DECODER (INVERTING)

M54HCT138
RAD HARD 3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED:
t_PD = 16ns (TYP.) at V_CC = 4.5V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s COMPATIBLE WITH TTL OUTPUTS:
V_IH = 2V (MIN.) V_IL = 0.8V (MAX)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 138
s DEVICE FULLY COMPLIANT WITH
SCC-9205-022
DESCRIPTION
The M54HCT138 is an high speed CMOS 3 TO 8
LINE DECODER fabricated with silicon gate
C²MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC138D
M54HC138K
EM
M54HC138D1
M54HC138K1
inhibited and all the 8 outputs go high. Three
enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
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