M54HCT138 Datasheet, PDF (1/10 Pages) STMicroelectronics – 3 TO 8 LINE DECODER INVERTING

M54HCT138
M74HCT138
3 TO 8 LINE DECODER (INVERTING)
. HIGH SPEED
t_PD = 16 ns (TYP.) at V_CC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA AT TA = 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. SYMMETRICAL OUTPUT IMPEDANCE
|I_OH| = I_OL
. COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN.) V_IL = 0.8V (MAX)
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS138
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HC138 is a high speed CMOS 3 TO 8
LINE DECODER fabricated in silicon gate C²MOS
technology. It has the same high speed perform-
ance of LSTTL combined with true CMOSlow power
consumption. If the device is enabled, 3 binary se-
lect inputs (A, B and C) determine which one of the
outputs will go low. If enable input G1 is held low or
either G2A or G2B is held high, the decoding func-
tion is inhibited and all the 8 outputs go high. Three
enable inputs are provided to ease cascade connec-
tion and application of address decoders for mem-
ory systems. All inputs are equipped with protection
circuits against static discharge and tran- sient ex-
cess voltage.This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC²MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption.
ORDER CODES :
M54HCT138F1R M74HCT138M1R
M74HCT138B1R M74HCT138C1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
February 1993
NC =
No Internal
Connection
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