M54HCT125 Datasheet, PDF (1/10 Pages) STMicroelectronics – QUAD BUS BUFFERS 3-STATE

M54/74HCT125
M54/74HCT126
QUAD BUS BUFFERS (3-STATE)
. HIGH SPEED
tPD = 12 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT 25 °C
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH = 6 mA (MIN.)
. COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN.) V_IL = 0.8V (MAX)
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS125/126
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT125/126 are high speed CMOS
QUAD BUS BUFFER (3-STATE) FABRICATED IN
SILICON GATE C²MOS technology. They have the
same high speed performance of LSTTL combined
with true CMOS low power consumption. These de-
vices require the same 3-STATE control input G to
be taken high to make the output go into the high im-
pedance state.This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC²MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
ORDER CODES :
M54HCTXXXF1R M74HCTXXXM1R
M74HCTXXXB1R M74HCTXXXC1R
PIN CONNECTIONS (top view)
HCT125
INPUT AND OUTPUT EQUIVALENT CIRCUIT
HCT126
October 1993
NC =
No Internal
Connection
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