M54HC77 Datasheet, PDF (1/10 Pages) STMicroelectronics – 4-BIT D-TYPE LATCH

. HIGH SPEED
tPD = 10 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 2 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS77
DESCRIPTION
The M54/74HC77 is a high speed CMOS 4-BIT D-
TYPE LATCH fabricated in silicon gate C²MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. It contains two groups of 2-bit latches con-
trolled by an enable input (G1 • 2 or G3 • 4). These
two latch groups can be used in different circuits. The
data applied to the data inputs (1D, 2D, or 3D, 4D) are
transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) re-
spectively when the enable input (G1 • 2 or G3 • 4) is
taken high. The Q outputs will follow the data inputs
as long as the enable input is kept high. When the en-
able input is taken low, the information data applied to
the data inputs is retained at the Q outputs. All inputs
are equipped with protection circuits against static dis-
charge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
M54HC77
M74HC77
4-BIT D-TYPE LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC77F1R
M 74H C7 7M 1R
M 74HC 77 B1 R
M 74H C7 7C 1R
PIN CONNECTIONS (top view)
October 1992
NC =
No Internal
Connection
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