M54HC76 Datasheet, PDF (1/11 Pages) STMicroelectronics – DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC76
M74HC76
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 65 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 2 µA (MAX.) AT 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
I_OH = I_OL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. HIGH NOISE IMMUNITY
V_NIH = V_NIL = 28 % V_CC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS76
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC76F1R
M 74H C7 6M 1R
M 74HC 76 B1 R
M 74H C7 6C 1R
DESCRIPTION
The M54/74HC76 is a high speed CMOS DUAL J-K
FLIP FLOP fabricated in silicon gate C²MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. Depending on with the logic level at the J
and K inputs this device changes state on the nega-
tive going transition of the clock pulse. CLEAR and
PRESET are independent of the clock and are ac-
complished by a logic low on the corresponding
input. All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
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