M54HC75 Datasheet, PDF (1/10 Pages) STMicroelectronics – 4 BIT D TYPE LATCH

M54HC75
RAD HARD 4 BIT D TYPE LATCH
s HIGH SPEED:
t_PD = 11ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 75
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9203-065
DESCRIPTION
The M54HC75 is an high speed CMOS 4 BIT D
TYPE LATCH fabricated with silicon gate C²MOS
technology.
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC75D
M54HC75K
EM
M54HC75D1
M54HC75K1
It contains two groups of 2 bit latches controlled by
an enable input (G1•2 or G3•4). These two latch
groups can be used in different circuits. Each latch
has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The
data applied to the data input is transferred to the
Q and Q outputs when the enable input is taken
high and the outputs will follow the data input as
long as the enable input is kept high. When the
enable input is taken low, the information data
applied to the data input is retained at the outputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/10