M54HC74_04 Datasheet, PDF (1/12 Pages) STMicroelectronics – RAD HARD DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

M54HC74
RAD HARD DUAL D TYPE FLIP FLOP
WITH PRESET AND CLEAR
s HIGH SPEED:
f_MAX = 67MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 74
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9203-050
DESCRIPTION
The M54HC74 is an high speed CMOS DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C²MOS technology.
DILC-14
FPC-14
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC74D
M54HC74K
EM
M54HC74D1
M54HC74K1
A signal on the D INPUT is transferred on the Q
OUTPUT during the positive going transition of the
clock pulse. CLEAR and PRESET are
independent of the clock and accomplished by a
low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/12