M54HC74 Datasheet, PDF (1/11 Pages) STMicroelectronics – DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

M54HC74
M74HC74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 71 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 2 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS74
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC74F1R
M 74H C7 4M 1R
M 74HC 74 B1 R
M 74H C7 4C 1R
DESCRIPTION
The M54/74HC74 is a high speed CMOS DUAL D
TYPE FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C²MOS technology. It has the
same high speed performance of LSTTL combined
with true CMOS low power consumption. A signal on
the D INPUT is transferred to the Q OUTPUT during
the positive going transition of the clock pulse.
CLEAR and PRESET are independent of the clock
and accomplished by a low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
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