M54HC73_04 Datasheet, PDF (1/11 Pages) STMicroelectronics – RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC73
RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
f_MAX = 80MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 73
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9203-071
DESCRIPTION
The M54HC73 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C²MOS technology.
DILC-14
FPC-14
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC73D
M54HC73K
EM
M54HC73D1
M54HC73K1
Depending on the logic level applied to J and K
inputs, this device changes state on the negative
going transition of clock input pulse (CK). The
clear function is accomplished independently of
the clock condition when the clear input (CLR) is
taken low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/11