M54HC597 Datasheet, PDF (1/13 Pages) STMicroelectronics – 8 BIT LATCH/SHIFT REGISTER

. HIGH SPEED
fMAX = 60 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS597
M54HC597
M74HC597
8 BIT LATCH/SHIFT REGISTER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 59 7F 1R
M 74H C5 97 M1 R
M 74HC 59 7B 1R
M 74H C5 97 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC597 is a high speed CMOS 8-BIT
LATCH/SHIFT REGISTER fabricated in silicon gate
C²MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption.
This devices comes in a 16-pin package and consist
of an 8-bit storage latch feeding a parallel-in, serial-
out 8-bit shift register. Both the storage register and
shift register have positive-edge triggered clocks.
The shift register also has direct load (from storage)
and clear inputs.
All inputs are equipped with protection circuits
against static discharge and transient voltage ex-
cess.
NC =
No Internal
Connection
October 1992
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