M54HC595_04 Datasheet, PDF (1/15 Pages) STMicroelectronics – RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

M54HC595
RAD-HARD 8 BIT SHIFT REGISTER
WITH OUTPUT LATCHES (3 STATE)
s HIGH SPEED:
f_MAX = 59MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 6mA (MIN.) FOR QA to QH
|I_OH| = I_OL = 4mA (MIN.) FOR QH’
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 595
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9306-051
DESCRIPTION
The M54HC595 is an high speed CMOS 8-BIT
SHIFT REGISTERS/OUTPUT LATCHES
(3-STATE) fabricated with silicon gate C²MOS
technology.
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC595D
M54HC595K
EM
M54HC595D1
M54HC595K1
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. The storage register has 8 3-STATE
outputs. Separate clocks are provided for both the
shift register and the storage register.
The shift register has a direct-overriding clear,
serial input, and serial output (standard) pins for
cascading. Both the shift register and storage
register use positive-edge triggered clocks. If both
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/15