M54HC573_04 Datasheet, PDF (1/12 Pages) STMicroelectronics – RAD-HARD OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

M54HC573
RAD-HARD OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
t_PD = 13ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 6mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 573
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9202-072
DESCRIPTION
The M54HC573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C²MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
PIN CONNECTION
DILC-20
FPC-20
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC573D
M54HC573K
EM
M54HC573D1
M54HC573K1
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while is at high level the outputs will be
in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
May 2004
Rev. 1
1/12