M54HC51 Datasheet, PDF (1/9 Pages) STMicroelectronics – DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE

M54HC51
M74HC51
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
. HIGH SPEED
tPD = 10 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 1 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS51
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC51F1R
M 74H C5 1M 1R
M 74HC 51 B1 R
M 74H C5 1C 1R
DESCRIPTION
The M54/74HC51 is a high speed CMOS DUAL 2
WIDE-2 INPUT AND/OR INVERT GATE fabricated
in silicon gate C²MOS technology. It has the same
high speed performance of LSTTL combined with
true CMOS low power consumption. It contains a 2-
WIDE 2-INPUT AND-OR-INVERT GATE and a 2-
WIDE 3-INPUT AND-OR-INVERT GATE.
The internal circuit is composed of 3 stages (2-
INPUT) or 5 stages (3-INPUT) including buffered
output, which gives high noise immunity and a
stable output. All inputs are equipped with protection
circuits against static discharge and transient ex-
cess voltage.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
December 1992
NC =
No Internal
Connection
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