M54HC4514 Datasheet, PDF (1/10 Pages) STMicroelectronics – RAD-HARD 4 TO 16 LINE DECODER/LATCH

M54HC4514
RAD-HARD 4 TO 16 LINE DECODER/LATCH
s HIGH SPEED:
t_PD= 20 ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 4514
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9205-019
DESCRIPTION
The M54HC4514 is an high speed CMOS 4 LINE
TO 16 LINE SEGMENT DECODER WITH
LATCHED INPUTS fabricated with silicon gate
C²MOS technology.
A binary code stored in the four input latches (A to
D) provides a high level at the selected one of
PIN CONNECTION
DILC-24
FPC-24
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC4514D
M54HC4514K
EM
M54HC4514D1
M54HC4514K1
sixteen outputs excluding the other fifteen outputs,
when the inhibit input (INHIBIT) is held low. When
the inhibit input (INHIBIT) is held high, all outputs
are kept low level, while the latch function is
available. The data applied to the data inputs are
transferred to the Q outputs of latches when the
strobe input is held high. When the strobe input is
taken low, the information data applied to the data
input at a time is retained at the output of the
latches.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
May 2004
Rev. 1
1/10