M54HC4040 Datasheet, PDF (1/11 Pages) STMicroelectronics – RAD-HARD 12 STAGE BINARY COUNTER

M54HC4040
RAD-HARD 12 STAGE BINARY COUNTER
s HIGH SPEED:
f_MAX = 70 MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 4040
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9204-069
DESCRIPTION
The M54HC4040 is an high speed CMOS 12
STAGE BINARY COUNTER fabricated with
silicon gate C²MOS technology.
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC4040D
M54HC4040K
EM
M54HC4040D1
M54HC4040K1
A clear input is used to reset the counter to the all
low level state. A high level on CLEAR
accomplishes the reset function. A negative
transition on the CLOCK input increments the
counter by one.
For M54HC4040 each division stage has an
output; the final frequency is 1/4096 f_IN.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
May 2004
Rev. 1
1/11