M54HC4020 Datasheet, PDF (1/13 Pages) STMicroelectronics – HC4020 14 STAGE BINARY COUNTER HC4040 12 STAGE BINARY COUNTER

M54/74HC4020
M54/74HC4040
HC4020 14 STAGE BINARY COUNTER
HC4040 12 STAGE BINARY COUNTER
. HIGH SPEED
f_MAX = 73 MHz (TYP.) at V_CC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 ^oC
. HIGH NOISE IMMUNITY
V_NIH = V_NIL = 28 % V_CC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|I_OH| = I_OL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
V_CC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
4020B/4040B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
DESCRIPTION
The M54/74HC4020/HC4040 are high speed
CMOS 14/12-STAGE BINARY COUNTER
fabricated in silicon gate C²MOS technology. They
have the same high speed performance of LSTTL
combined with true CMOS low consumption.
A clear input is used to reset the counter to the all
low level state. A high level on CLEAR accomplishes
the reset function. A negative transition on the
CLOCK input increments the counter by one.
The maximum division available at last stage is
1/16384 x f_IN at clock.
For HC4040 each division stage has an output; the
final frequency is 1/4096 x fIN.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
For HC4020 twelve kind od divided output are
provided; 1st and 4th stage to 14th stage.
PIN CONNECTION (top view)
HC4020
HC4040
HC4020
HC4040
March 1993
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