M54HC4017 Datasheet, PDF (1/12 Pages) STMicroelectronics – DECADE COUNTER/DIVIDER

M54HC4017
M74HC4017
. HIGH SPEED
tPD = 21 ns (typ.) AT VCC = 5V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 ^oC
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLEWITH
4017B
DECADE COUNTER/DIVIDER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC4017F1R M74HC4017M1R
M74HC4017B1R M74HC4017C1R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC4017 is a high speed CMOS DE-
CADE COUNTER/DIVIDER fabricated in silicon
gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
The M54/74HC4017 is a 5-stage Johnson counter
with 10 decoded outputs. Each of the decoded out-
puts is normally low and sequentially goes high on
the low to high transition of the clock input. Each out-
put stays high for one clock period of the 10 clock
period cycle. The CARRY output goes low to high
after OUTPUT 10 goes low, and can be used in con-
junction with the CLOCK ENABLE to cascade sev-
eral stages.
The CLOCK ENABLE input disables counting when
in the high state. A RESET input is also provided
which when taken high sets all the decoded outputs
low.
Q3
NC =
No Internal
Connection
October 1992
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