M54HC375 Datasheet, PDF (1/11 Pages) STMicroelectronics – QUAD D TYPE LATCH

. HIGH SPEED
tPD = 14 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 1 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS375
M54HC375
M74HC375
QUAD D TYPE LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 37 5F 1R
M 74H C3 75 M1 R
M 74HC 37 5B 1R
M 74H C3 75 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC375 is a high speed CMOS QUAD D
TYPE LATCH fabricated in silicon gate C²MOS
technology. It has the same high speed perform-
ance of LSTTL combined with true CMOSlow power
consumption. It contains two groups of 2-bit latches
controlled by an enable input (G1 ^. 2 or G3 ^. 4).
These two latch groups can be used in the different
circuits. Each latch has Q and Q outputs (1Q to 4Q
and 1Q to 4Q). The data applied to the data input is
transferred to the Q and Q outputs when the enable
input is taken high and the outputs will follow the
data input as long as the enable input is kept high.
When the enable input is taken low, the information
data applied to the data input at that time is retained
at the outputs.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
NC =
No Internal
Connection
February 1993
1/11