M54HC374 Datasheet, PDF (1/11 Pages) STMicroelectronics – OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING

M54HC374
RAD-HARD OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
f_MAX = 90MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 6mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 374
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9203-060
DESCRIPTION
The M54HC374 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate C²MOS technology.
This 8 bit D-TYPE FLIP FLOP is controlled by a
clock input (CK) and an output enable input (OE).
PIN CONNECTION
DILC-20
FPC-20
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC374D
M54HC374K
EM
M54HC374D1
M54HC374K1
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is high the outputs will be in a
high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
May 2004
Rev. 1
1/11