M54HC279 Datasheet, PDF (1/10 Pages) STMicroelectronics – QUAD S - R LATCH

. HIGH SPEED
tPD = 12 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 2 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS279
DESCRIPTION
The M54/74HC279 is a high speed CMOS QUAD S
- R LATCH fabricated in silicon gate C²MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
M54HC279
M74HC279
QUAD S - R LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 27 9F 1R
M 74H C2 79 M1 R
M 74HC 27 9B 1R
M 74H C2 79 C1 R
PIN CONNECTIONS (top view)
March 1993
NC =
No Internal
Connection
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