M54HC242 Datasheet, PDF (1/11 Pages) STMicroelectronics – QUAD BUS TRANSCEIVER 3-STATE

M54/74HC242
M54/74HC243
QUAD BUS TRANSCEIVER (3-STATE)
. HIGH SPEED
tPD = 9 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT 25 °C
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH = 6 mA (MIN.)
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
V_CC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS242/243
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
The M54/74HC242/243 are high speed CMOS
QUAD BUS TRANSCEIVER (3-STATE)
FABRICATED IN SILICON GATE C²MOS
technology. They have the same high speed
performance of LSTTL combined with true CMOS
low power consumption. The HC242/243 are 3
STATE bi-directional inverting and non-inverting
buffers and are intended for two-way asynchronous
communication between data buses. They are high
drive current outputs which enable high speed
operation when driving large bus capacitances.
Each device has one active high enable (GBA), and
one active low enable (GAB). GBA enables the A
outputs and GAB enables the B outputs. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
PIN CONNECTIONS (top view)
HC242
INPUT AND OUTPUT EQUIVALENT CIRCUIT
HC243
October 1993
NC =
No Internal
Connection
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