M54HC238 Datasheet, PDF (1/10 Pages) STMicroelectronics – 3 TO 8 LINE DECODER

. HIGH SPEED
tPD = 14 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS238
M54HC238
M74HC238
3 TO 8 LINE DECODER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 23 8F 1R
M 74H C2 38 M1 R
M 74HC 23 8B 1R
M 74H C2 38 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC238 is a high speed CMOS 3 to 8 line
decoder fabricated in silicon gate C²MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption. If
the device is enabled, 3 binary select inputs (A, B and
C) determine which one of outputs will go high. Enable
input G1 is held ”Low” or either G2A or G2B is held
”High” decoding function is inhibited and all the 8 out-
puts go low. Three enable inputs are provided to ease
cascade connection and application of this address
decoder in memory systems.
All inputs are equipped with protection circuits against
static discharge and transient excess voltage.
NC =
No Internal
Connection
October 1993
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