M54HC237 Datasheet, PDF (1/11 Pages) STMicroelectronics – 3 TO 8 LINE DECODER LATCH

. HIGH SPEED
tPD = 12 ns (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS237
M54HC237
M74HC237
3 TO 8 LINE DECODER LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 23 7F 1R
M 74H C2 37 M1 R
M 74HC 23 7B 1R
M 74H C2 37 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC237 is a high speed CMOS 3 TO 8
LINE DECODER LATCH fabricated in silicon gate
C²MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
When GL goes from low to high, the address present
at the select inputs (A, B, C) is stored in the latches.
As long as GL remains high no address changes will
be recognized. Output enable controls, G1 and G2
control the state of the outputs independantly of the
select or latch-enable inputs. All of the outputs are low
unless G1 is high and G2 is low. The ’HC237 is ideally
suited for the implementation of glitch-free decoders
in stored-address applications in bus oriented sys-
tems. All inputs are equipped with protection circuits
against static discharge and transient excess voltage.
NC =
No Internal
Connection
October 1992
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