M54HC175_04 Datasheet, PDF (1/10 Pages) STMicroelectronics – RAD-HARD QUAD D-TYPE FLIP FLOP WITH CLEAR

M54HC175
RAD-HARD QUAD D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
t_PD = 16 ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 175
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9203-052
DESCRIPTION
The M54HC175 is an high speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C²MOS technology.
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC175D
M54HC175K
EM
M54HC175D1
M54HC175K1
These four flip-flops are controlled by a clock input
(CLOCK) and a clear input (CLEAR). The
information data applied to the D inputs (1D to 4D)
are transferred to the outputs (1Q to 4Q and 1Q to
4Q) on the positive-going edge of the clock pulse.
The reset function is accomplished when the
CLEAR input is low and all Q outputs are low
regardless of other input conditions.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
April 2004
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