M54HC173 Datasheet, PDF (1/12 Pages) STMicroelectronics – QUAD D-TYPE REGISTER 3-STATE

M54HC173
M74HC173
QUAD D-TYPE REGISTER (3-STATE)
. HIGH SPEED
fMAX = 73 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) at T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS 173
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 17 3F 1R
M 74H C1 73 M1 R
M 74HC 17 3B 1R
M 74H C1 73 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC173 is a high speed CMOS QUAD D-
TYPE REGISTER (3-STATE) fabricated in silicon
gate C²MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device is composed of a four-bit register includ-
ing D-type flip-flops and 3-state buffers. The four flip-
flops are controlled by a common clock input
(CLOCK) and a common reset input (CLEAR). Sig-
nals applied to the data inputs (D₁-D₄) are stored at
the respective flip-flops on the positive going transi-
tion of the clock input, only when both clock control
inputs (G₁ and G₂) are held low.
The reset feature is asynchronous and active high.
The stored data are provided on each output only
when both output control inputs (M and N) are held
low, otherwise the outputs go to the high-impedance
state.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
NC =
No Internal
Connection
October 1992
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