M54HC166_04 Datasheet, PDF (1/11 Pages) STMicroelectronics – RAD-HARD 8 BIT PISO SHIFT REGISTER

M54HC166
RAD-HARD 8 BIT PISO SHIFT REGISTER
s HIGH SPEED:
f_MAX = 63 MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =4µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 166
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9306-043
DESCRIPTION
The M54HC166 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C²MOS technology.
It consists of parallel or serial inputs and a
serial-out 8 bit shift register with gated clock inputs
and an overriding clear input. The parallel-in or
serial-in modes are controlled by the SHIFT/LOAD
PIN CONNECTION
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC166D
M54HC166K
EM
M54HC166D1
M54HC166K1
input. When the SHIFT/LOAD input is held high,
the serial data input is enabled and the eight
flip-flops perform serial shifting with each clock
pulse; when held low, the parallel data inputs are
enabled and synchronous loading occurs on the
next clock pulse. Clocking is accomplished on the
low-to-high level edge of the clock pulse. The
CLOCK-INHIBIT input should be changed to the
high only while the clock input is held high. A direct
clear input overrides all other inputs, including the
clock, and sets all flip-flops to zero. Functional
details are shown in the truth table and the timing
chart. All inputs are equipped with protection
circuits against static discharge and transient
excess voltage.
March 2004
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