M54HC166 Datasheet, PDF (1/13 Pages) STMicroelectronics – 8 BIT PISO SHIFT REGISTER

M54HC166
M74HC166
. HIGH SPEED
fMAX = 57 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS166
8 BIT PISO SHIFT REGISTER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 16 6F 1R
M 74H C1 66 M1 R
M 74HC 16 6B 1R
M 74H C1 66 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC166 is a high speed C²MOS 8 BIT
PISO SHIFT REGISTER fabricated in silicon gate
C²MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption.
It consists of parallel or serial inputs and a serial-out
8-bit shift register with gated clock inputs and an
overriding clear input. The parallel-in or serial-in
modes are controlled by the SHIFT/LOAD input.
When the SHIFT/LOAD input is held high, the serial
data input is enabled and the eight flip-flops perform
serial shifting with each clock pulse. When held low,
the parallel data inputs are enabled and syn-
chronous loading occurs on the next clock pulse.
Clocking is accomplished on the low-to-high level
edge of the clock pulse. The CLOCK-INHIBIT input
should be changed to the high only while the
CLOCK input is held high. A direct clear input over-
rides all other inputs, including the clock, and sets
all flip-flops to zero. Functional details are shown in
the truth table and the timing chart.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
NC =
No Inter-
nal Con-
October 1992
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