M54HC138 Datasheet, PDF (1/10 Pages) STMicroelectronics – 3 TO 8 LINE DECODER INVERTING

M54HC138
M74HC138
3 TO 8 LINE DECODER (INVERTING)
. HIGH SPEED
tPD = 16 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA AT T_A = 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL
. HIGH NOISE IMMUNITY
V_NIH = V_NIL = 28 % V_CC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS138
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 13 8F 1R
M 74H C1 38 M1 R
M 74HC 13 8B 1R
M 74H C1 38 C1 R
The M54/74HC138 is a high speed CMOS 3 TO 8
LINE DECODER fabricated in silicon gate C²MOS
technology.
PIN CONNECTIONS (top view)
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
If the device is enabled, 3 binary select inputs (A, B
and C) determine which one of the outputs will go
low. If enable input G1 is held low or either G2A or
G2B is held high, the decoding function is inhibited
and all the 8 outputs go high.
Three enable inputs are provided to ease cascade
connection and application of address decoders for
memory systems. All inputs are equipped with pro-
tection circuits against static discharge and tran-
sient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
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