M54HC137_04 Datasheet, PDF (1/10 Pages) STMicroelectronics – RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)

M54HC137
RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)
s HIGH SPEED:
t_PD =18ns (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC = 2µA (MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 137
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9205-013
DESCRIPTION
The M54HC137 is an high speed CMOS 3 TO 8
LINE DECODER/LATCH (INVERTING) fabricated
with silicon gate C²MOS technology.
This device is a 3 to 8 line decoder with latches on
the three address inputs. When GL goes from low
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC137D
M54HC137K
EM
M54HC137D1
M54HC137K1
to high, the addresses present at the select inputs
(A, B, and C) is stored in the latches. As long as
GL remains high no address changes will be
recognized. Output enable pins G1 and G2,
control the state of the outputs independently of
the select or latch-enable inputs. All the outputs
are high unless G1 is high and G2 is low. The
54HC137 is ideally suited for the implementation
of glitch-free decoders in stored-address
application in bus oriented systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
March 2004
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