M54HC131 Datasheet, PDF (1/12 Pages) STMicroelectronics – 3 TO 8 LINE DECODER/LATCH

M54HC131
M74HC131
3 TO 8 LINE DECODER/LATCH
. HIGH SPEED
tPD = 22 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) at T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
| IOH | = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC(OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS131
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 13 1F 1R
M 74H C1 31 M1 R
M 74HC 13 1B 1R
M 74H C1 31 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC131 is a high speed CMOS 3 TO 8
LINE DECODER/LATCH fabricated in silicon gate
C2MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device is a DECODER/LATCH capable of se-
lecting arbitrarily one of eight outputs by three binary
inputs A, B, and C, in this case, the selected output
is at logic ”low”.
Also, when ENABLE input G1 is set low or ENABLE
input G2 is set high, selection is inhibited regardless
of other input signals and all the outputs are at high.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
NC =
No Internal
Connection
October 1992
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