M54HC113 Datasheet, PDF (1/11 Pages) STMicroelectronics – DUAL J-K FLIP FLOP WITH PRESET

M54HC113
M74HC113
DUAL J-K FLIP FLOP WITH PRESET
. HIGH SPEED
fMAX = 71 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
I_CC = 2 µA at T_A = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
t_PLH = t_PHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS113
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 11 3F 1R
M 74H C1 13 M1 R
M 74HC 11 3B 1R
M 74H C1 13 C1 R
The M54/74HC113 is a high speed CMOS DUAL J-
K FLIP FLOP WITH PRESET fabricated in silicon
gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption. This circuit offers in-
dividual J, K, set, and clock inputs. These monolithic
dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH
and the bistable will function as shown in the truth
table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on
the negative-going edge of the clock pulse. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
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