M54HC109_04 Datasheet, PDF (1/10 Pages) STMicroelectronics – RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC109
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED :
f_MAX = 67MHz (TYP.) at V_CC = 6V
s LOW POWER DISSIPATION:
I_CC =2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 109
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9306-048
DESCRIPTION
The M54HC109 is an high speed CMOS DUAL
J-K FLIP FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C²MOS technology. In
accordance with the logic level on the J and K
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC109D
M54HC109K
EM
M54HC109D1
M54HC109K1
input this device changes state on positive going
transition of the clock pulse. CLEAR and PRESET
are independent of the clock and are
accomplished by a logic low on the corresponding
input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
March 2004
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