M48Z512A_10 Datasheet, PDF (1/21 Pages) STMicroelectronics – 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM

M48Z512A
M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER^® SRAM
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
WRITE cycles
■ 10 years of data retention in the absence of
power
■ Automatic power-fail chip deselect and WRITE
protection
■ Two WRITE protect voltages:
(V_PFD = power-fail deselect voltage)
– M48Z512A:
V_CC = 4.75 to 5.5 V, 4.5 V ≤ V_PFD ≤ 4.75 V
– M48Z512AY:
V_CC = 4.5 to 5.5 V, 4.2 V ≤ V_PFD ≤ 4.5 V
– M48Z512AV:
V_CC = 3.0 to 3.6 V, 2.8 V ≤ V_PFD ≤ 3.0 V
M48Z512AV not for new design (see
M48Z512BV). Contact ST sales office for
availability.
■ Battery internally isolated until power is applied
■ Pin and function compatible with JEDEC
standard 512 K x 8 SRAMs
■ PMDIP32 is an ECOPACK^® package
■ RoHS compliant
– Lead-free second level interconnect
32
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PMDIP32 module (PM)
Description
The M48Z512A/Y/V ZEROPOWER^® RAM is a
non-volatile, 4,194,304-bit static RAM organized
as 524,288 words by 8 bits. The devices combine
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP Module.
August 2010
Doc ID 5146 Rev 8
1/21
www.st.com
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